1. Technical Field
The present invention relates generally to a method, system, and product for obtaining optimal timing in a data path that includes variable delay lines and coupled endpoints.
2. Description of the Related Art
Today, the design of most digital integrated circuits (IC's) is a highly structured process based on an HDL (Hardware Description Language) methodology. FIG. 1 illustrates a simplified flowchart representation of an IC design cycle. First, block 102 depicts specifying the IC to be designed. Then, the IC design is reduced to an HDL code, as illustrated by block 104. This level of design abstraction is referred to as the Registered Transfer Level (RTL), and is typically implemented using an HDL language such as Verilog-HDL (“Verilog”) or VHDL. At the RTL level of abstraction, the IC design is specified by describing the operations that are performed on data as it flows between circuit inputs, outputs, and clocked registers. The RTL level description is referred to as the RTL code, which is generally written in Verilog or in VHDL.
The IC design, as expressed by the RTL code, is then synthesized to generate a gate-level description, or a netlist, as depicted by block 106. Synthesis is the step taken to translate the architectural and functional descriptions of the design, represented by RTL code, to a lower level of representation of the design such as a logic-level and gate-level descriptions. The IC design specification and the RTL code are technology independent. That is, the specification and the RTL code do not specify the exact gates or logic devices to be used to implement the design. However, the gate-level description of the IC design is technology dependent. This is because during the synthesis process, the synthesis tool uses a given technology library, as depicted by block 108, to map the technology independent RTL code into technology dependent gate-level netlists.
After the synthesis of the design, the gate-level netlist is verified, as depicted by block 110, and the layout of the circuit is determined as illustrated by block 112. The IC is then fabricated as depicted by block 114.
At the RTL level, designers must make all key design decisions such as design hierarchy and partitioning, clocking scheme, reset scheme, and locations of registers. All those decisions are contained and reflected in the RTL code. The RTL code is technology independent, as well as independent from design tools. As a result, some characteristics of the RTL code can strongly influence further design steps, including logic synthesis, gate-level simulation, static timing analysis, test insertion and layout. Unexpected problems and difficulties with the IC design can be encountered at any of these steps and cause implementation obstacles impacting project schedules and costs.
Encountered late in the design cycle, problems with the design can greatly impact project schedules and design cost. The later the problems are discovered, the more significant the impact and the higher the cost in time and expenditure to correct the error. For example, timing or routability problems encountered during layout can require a new run through logic synthesis, gate-level verification, and test logic insertion. Several iterations through synthesis and physical design are usually needed before converging to correct post-layout timing problems.
FIG. 2 depicts an example of a data path that may be included within an integrated circuit in accordance with the prior art. The illustrated data path includes delay lines and coupled endpoints. The data path has a start point at the pad Data 200 and is coupled to coupled endpoints, flip-flop 216 and flip-flop 222, through logic 202, software programmable delay line 204, logic 206, variable delay line with hardware taps 208, and logic 210.
Throughout the following description, flip-fop 216 is referred to as FF0 having a data input FF0/D and a clock input FF0/CP. Flip-fop 222 is referred to as FF1 having a data input FF1/D and a clock input FF1/CP.
Logic 212 may be included prior to the data input FF0/D into flip-flop 216. Logic 218 may be included prior to the data input FF1/D into flip-flop 222. Logic 214 may be included prior to the clock input FF0/CP into flip-flop 216. And, logic 220 may be included prior to the clock input FF1/CP into flip-flop 222. Programmable delay line 204 is a software programmable delay by using the SEL input port 204a. Variable delay line 208 uses hardware adjustable taps to alter its amount of delay. The flip-flop inputs FF0/CP and FF1/CP are clocked by the pad Clock 224. Additional logic 226 may be included after clock 224.
Those skilled in the art will recognize that one or more of the logic blocks 202, 206, 210, 212, 214, 218, 220, and 226 may or may not be included in the design.
The data signals depicted by FIGS. 3-5 are generated by data 200, and the clock signals are generated by clock 224 (see FIG. 2).
FIG. 3 illustrates an ideal timing diagram with equal data setup and hold times relative to the clock signal. At time t, the data window 300 has an equal data setup and hold time relative to the clock signal. Typical software synthesis programs will only optimize the data path shown in FIG. 2 until passing slack times, i.e. setup and hold time margins, are obtained at the coupled endpoints FF0/D and FF1/D. Thus, the data windows for FF0/D and FF1/D could be offset as depicted by data windows 400 and 402 shown in FIG. 4. Inaccuracies in delay line models and wireload models used during synthesis, and clock-tree balancing over best, nominal, and worst operating conditions could possibly cause the post-layout circuit to have one of the coupled endpoints failing either setup or hold times. For example, as illustrated by FIG. 5, data window 500 fails hold time while data window 502 meets the setup and hold times.
Therefore, in the prior art, although the setup and hold times are optimized for the coupled endpoints together, after the layout step, errors could still be present. For example, such as depicted by FIG. 5, one of the endpoints could fail timing although the coupled endpoints together met timing requirements during the synthesis step.
Therefore, a need exists for a method, system, and product for obtaining optimal timing post-layout for a data path that includes variable delay lines and coupled endpoints.